1. Field of the Invention
The present invention relates to a chip package structure, and in particular relates to a chip package structure formed by a wafer-level process and a manufacturing method thereof.
2. Description of the Related Art
Along with tendency towards light, thin, short, and small electronic devices, semiconductor chip package structures accordingly tend to be multi-chip package (MCP) structures to achieve requirements of multi-function and high performance. Multi-chip package (MCP) structures integrate a variety of semiconductor chips in a single package, such as logic chips, analog chips, control chips, or memory chips.
Multi-chip package structures may be fabricated by a wafer-level packaging process. For example, different kinds of semiconductor wafers may be stacked and bonded to each other to form a wafer stacking structure. Then, the wafer stacking structure is cutted to form a plurality of multi-chip package structures. However, because the portion of the wafer contacting the cutting knife is easy to be damaged due to high stress, edges of chips of the multi-chip package structures usually suffer problems of damaged vertex or cracks.